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Preliminary Technical Data
SUMMARY
High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Code compatible with all other SHARC DSPs The ADSP-21267 processes high performance audio while enabling low system costs Audio decoders and post processor-algorithms support. Non-volatile memory can be configured to contain a combination of PCM 96 kHz, Dolby Digital, Dolby Digital EX2, Dolby Pro Logic IIx, DTS 5.1, DTS ES Discrete 6.1, DTS-ES Matrix 6.1, DTS Neo:6, MPEG2x BC (2 channel) and others. See www.analog.com/SHARC for a complete list Single-Instruction Multiple-Data (SIMD) computational architecture--two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating point computational units, each with a multiplier, ALU, shifter, and register file High bandwidth I/O --a parallel port, an SPI port, four serial ports, a digital audio interface (DAI) and JTAG test port
SHARC(R) Processor ADSP-21267
DAI incorporates two precision clock generators (PCG), and an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU) On-chip memory--1M Bit of on-chip SRAM and a dedicated 3M Bits of on-chip mask-programmable ROM The ADSP-21267 is available with a 150 MHz core instruction rate. For complete ordering information, see Ordering Guide on page 43
Figure 1. FUNCTIONAL BLOCK DIAGRAM
CORE P ROCE SSO R INSTRUCTION CACHE 32 X 48-BIT
DUAL PORTED MEMORY BLOCK 0 S RAM 0.5 MBI T
DUAL P ORT ED ME MORY BLOCK 1
S RAM 0.5 MBIT
TIMER
ROM 1.5 MBIT
RO M 1.5 MBI T
DAG1 8X4X32
DAG 2 8X 4X32
PROG RAM SEQ UE NCE R
ADDR
DATA
ADDR
DATA
32 PM ADDRE SS BUS DM ADDRESS BUS 64 64 P M DATA BUS DM DATA BUS
IO D (32) IOA (18)
32
PX REGIS TER
P ROCE SSI NG ELEME NT (PE X) PRO CE SSI NG ELEMENT (PEY )
DMA CONTROLLER
2 2 C HA N N ELS
GPIO FLAG S/ IRQ /TIMEXP
4
4
S PI PORT (1)
A D D RE SS/ D A TA B U S/ GP IO
16 3
6 JTAG TES T & EMULATIO N
20 SIG NAL ROUTING UNIT
SERIAL P ORTS (6) INPUT DATA P ORTS (8) P ARALLEL DATA ACQUIS ITION PO RT PRE CI SION CLOCK G ENERATO RS (2) 3 TI ME RS (3)
I OP REGIS TERS (MEMO RY MAP PED) CONTROL, STATUS, & DAT A BUFFERS
CON TR OL/G PIO
PARALLEL PORT
S
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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PRELIMINARY TECHNICAL DATA ADSP-21267
KEY FEATURES
At 150 MHz (6.65 ns) core instruction rate, the ADSP-21267 operates at 900 MFLOPS performance whether operating on fixed or floating point data 300 MMACS sustained performance at 150 MHz Code compatibility--At assembly level, uses the same instruction set as other SHARC DSPs Super Harvard Architecture--three independent buses for dual data fetch, instruction fetch, and nonintrusive, zerooverhead I/O 1M Bit on-chip dual-ported SRAM (0.5M Bit in block 0 and 0.5M Bit in block 1) for simultaneous access by core processor and DMA 3M Bits on-chip dual-ported mask-programmable ROM (1.5M Bits in block 0 and 1.5M Bits in block 1) Dual Data Address Generators (DAGs) with modulo and bitreverse addressing Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing Single Instruction Multiple Data (SIMD) architecture provides: Two computational processing elements Concurrent execution-- Each processing element executes the same instruction, but operates on different data DMA Controller supports: 18 zero-overhead DMA channels for transfers between ADSP-21267 internal memory and the four serial ports, the input data port (IDP) , SPI-compatible port, and the parallel port 32-bit background DMA transfers at core clock speed, in parallel with full-speed processor execution Asynchronous parallel/external port provides: Access to asynchronous external memory 16 multiplexed address/data lines that can support 24-bit address external address range with 8-bit data or 16-bit address external address range with 16-bit data 50 Mbyte per sec transfer rate 256 word page boundaries External memory access in a dedicated DMA channel 8- to 32- bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital Audio Interface (DAI) includes four serial ports, two precision clock generators, an input data port/parallel data acquisition port, three timers and a signal routing unit Serial Ports provide: Four dual data line serial ports that operate at 37.5M Bits/s on each data line --each has a clock, frame sync and two data lines that can be configured as either a receiver or transmitter pair Left-justified Sample Pair and I2S Support, programmable direction for up to 16 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for newer telephony interfaces such as H.100/H.110 Up to 4 full-duplex TDM streams, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input Data Port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port Supports receive audio channel data in I2S, Left-justified sample pair, or right-justified mode Signal Routing Unit (SRU) provides configurable and flexible connections between all DAI components, four serial ports, three timers, 10 interrupts, six flag inputs, six flag outputs, two precision clock generators, an input data port/parallel data acquisition port, and 20 SRU I/O pins (DAI_Px) Serial Peripheral Interface (SPI) Master or slave serial boot through SPI Full-duplex operation Master-Slave mode multi-master support Open drain outputs Programmable baud rates, clock polarities and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM Based Security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multiplier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Also available in lead-free packages
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PRELIMINARY TECHNICAL DATA ADSP-21267
GENERAL DESCRIPTION
The ADSP-21267 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices' Super Harvard Architecture. The ADSP-21267 is source code compatible with the ADSP-2136x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Single-Instruction, Single-Data) mode. Like other SHARC DSPs, the ADSP-21267 is a 32-bit/40-bit floating-point processor optimized for high performance audio applications with its dualported on-chip SRAM, mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI). As shown in the Functional Block Diagram on page 1, the ADSP-21267 uses two computational units to deliver a significant performance increase over previous SHARC processors on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the ADSP-21267 DSP achieves an instruction cycle time of 6.6 ns at 150 MHz. With its SIMD computational hardware, the ADSP-21267 can perform 900 MFLOPS running at 150 MHz. Table 1 shows performance benchmarks for the ADSP-21267. Table 1. ADSP-21267 Benchmarks (at 150 MHz)
Benchmark Algorithm 1024 Point Complex FFT (Radix 4, with reversal) FIR Filter (per tap)1 IIR Filter (per biquad)1 Matrix Multiply (pipelined) [3x3] x [3x1] [4x4] x [4x1] Divide (y/x) Inverse Square Root
1
* Three Programmable Interval Timers with PWM Generation, PWM Capture/Pulse width Measurement, and External Event Counter Capabilities * On-Chip dual-ported SRAM (1 Mbit) * On-Chip dual-ported, mask-programmable ROM (3 Mbits) * JTAG test access port * 8- or 16-bit Parallel port that supports interfaces to off-chip memory peripherals * DMA controller * Four full-duplex serial ports * SPI-compatible interface * Digital Audio Interface that includes two precision clock generators (PCG), an input data port (IDP), four serial ports, eight serial interfaces, a 20-bit synchronous parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (SRU) Figure 2 on page 4 shows one sample configuration of a SPORT using the precision clock generator to interface with an I2S ADC and an I2S DAC with a much lower jitter clock than the serial port would generate itself. Many other SRU configurations are possible.
Speed (at 150 MHz) 61.3 s 3.3 ns 13.3 ns 30 ns 53.3 ns 20 ns 30 ns
ADSP-21267 FAMILY CORE ARCHITECTURE
The ADSP-21267 is code compatible at the assembly level with the ADSP-2136x, ADSP-2116x, and with the first generation ADSP-2106x SHARC DSPs. The ADSP-21267 shares architectural features with the ADSP-2136x and ADSP-2116x SIMD SHARC family of DSPs, as detailed in the following sections.
SIMD Computational Engine
The ADSP-21267 contains two computational processing elements that operate as a Single-Instruction Multiple-Data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive audio algorithms. Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file.
Assumes two files in multichannel SIMD mode.
The ADSP-21267 continues SHARC's industry leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. These features include 1M bit dual-ported SRAM memory, 3M bits dual-ported ROM, an I/O processor that supports 18 DMA channels, four serial ports, an SPI interface, an external parallel bus, and Digital Audio Interface (DAI). The block diagram of the ADSP-21267 on page 1, illustrates the following architectural features: * Two processing elements, each containing an ALU, Multiplier, Shifter and Data Register File * Data Address Generators (DAG1, DAG2) * Program sequencer with instruction cache * PM and DM buses capable of supporting four 32-bit data transfers between memory and the core at every core processor cycle
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PRELIMINARY TECHNICAL DATA ADSP-21267
ADSP-21267
CLOCK 2 2 3 CLKIN X TAL CLK_CFG1-0 BOOTCFG1 -0 FLG3 -1
CLKOUT ALE AD1 5-0 LATCH ADDR DATA RD WR FLG 0 OE WE CS CONTROL DATA ADDRESS PARALLEL PORT RAM , ROM BOO T ROM I /O DEVI CE
ADC (OPTI ONAL) CLK FS S DAT
DAI_P1 DAI_ P2 DAI_ P3 S CLK0 S FS0 SRU DAI_P 18 DAI _P 19 DAI_ P2 0
DAC (OP TIONAL) CLK FS S DAT
S D0A S D0B SPO RT0 S PORT1 SP ORT2 SP ORT 3
CLK FS
DAI
RES ET
P CG A PCGB
JTAG 6
Figure 2. ADSP-21267 System Sample Configuration
Independent, Parallel Computation Units
Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multi-function instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21267 features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see the Figure 1 on page 1). With the ADSP-21267's separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle.
Instruction Cache
TheADSP-21267 includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective--only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and FFT butterfly processing.
Data Register File
A general purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2126x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0-R15 and in PEY as S0-S15.
Data Address Generators With Zero-Overhead Hardware Circular Buffer Support
The ADSP-21267's two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital
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PRELIMINARY TECHNICAL DATA ADSP-21267
signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-21267 contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wrap-around, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. the parallel port. Eighteen channels of DMA are available on the ADSP-21267 -- one for the SPI interface, eight via the serial ports, eight via the Input Data Port and one via the processor's parallel port. Programs can be downloaded to the ADSP-21267 using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP21267 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory; all in a single instruction.
Digital Audio Interface (DAI)
The Digital Audio Interface (DAI) provides the ability to connect various peripherals to any of the DSPs DAI pins (DAI_P[20:1]). Programs make these connections using the Signal Routing Unit (SRU, shown in the block diagram on page 1). The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with nonconfigurable signal paths. The DAI also includes 4 serial ports, 2 precision clock generators (PCG), an input data port (IDP), 6 flag outputs and 6 flag inputs, and 3 timers. The IDP provides an additional input path to the ADSP-21267 core, configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port Each data channel has its own DMA channel that is independent from the ADSP21267's serial ports. For complete information on using the DAI, see the ADSP2126x SHARC DSP Peripherals Manual.
ADSP-21267 MEMORY AND I/O INTERFACE FEATURES
The ADSP-21267 adds the following architectural features to the SIMD SHARC family core:
Dual-Ported On-Chip Memory
The ADSP-21267 contains one megabit of internal SRAM and three megabits of internal mask-programmable ROM. Each block can be configured for different combinations of code and data storage (see ADSP-21267 Memory Map on page 6). Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor. The dualported memory, in combination with three separate on-chip buses, allow two data transfers from the core and one from the I/O processor, in a single cycle. On the ADSP-21267, the SRAM can be configured as a maximum of 32K words of 32-bit data, 64K words of 16-bit data, 21K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to one megabit. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one dedicated to each memory block assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.
Serial Ports
The ADSP-21267 features four full duplex synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as the AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock and frame sync. The data lines can be programmed to either transmit or receive and each data line has its own dedicated DMA channel. Serial ports are enabled via 8 programmable and simultaneous receive or transmit pins that support up to 16 transmit or 16 receive channels of audio data when all four SPORTS are enabled, or four full duplex TDM streams of 128 channels per frame. The serial ports operate at up to one-quarter of the DSP core clock rate, providing each with a maximum data rate of 37.5 Mbits/s for a 150 MHz core. Serial port data can be automatically transferred to and from on-chip memory via a dedicated DMA. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared. Serial ports operate in four modes: * Standard DSP serial mode * Multichannel (TDM) mode
DMA Controller
The ADSP-21267's on-chip DMA controller allows zero-overhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-21267's internal memory and its serial ports, the SPI-compatible (serial peripheral interface) port, the IDP (input data port/parallel data acquisition port) or
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PRELIMINARY TECHNICAL DATA ADSP-21267
INTERNAL MEMORY SPACE
LONG WORD ADDRESSING
IOP REGISTERS 0x0000 0000 - 0x0003 FFFF BLOCK 0 SRAM (0.5 Mbit) 0x0004 0000 - 0x0004 1FFF RESERVED 0x0004 2000 - 0x0005 7FFF BLOCK 0 ROM (1.5 mbit) 0x0005 8000 - 0x0002 FFFF RESERVED 0x0005 3000 - 0x0005 FFFF BLOCK 1 SRAM (0.5 Mbit) 0x0006 0000 - 0x0006 1FFF RESERVED 0x0006 2000 - 0x0007 7FFF BLOCK 1 ROM (1.5 mbit) 0x0007 8000 - 0x0007 DFFF RESERVED 0x0007 E000 - 0x0007 FFFF
NORMAL WORD ADDRESSING
IOP REGISTERS 0x0000 0000 - 0x0003 FFFF BLOCK 0 SRAM (0.5 Mbit) 0x0008 0000 - 0x0008 3FFF RESERVED 0x0008 4000 - 0x000A FFFF BLOCK 0 ROM (1.5 mbit) 0x000B 0000 - 0x000B BFFF RESERVED 0x000B C000 - 0x000B FFFF BLOCK 1 SRAM (0.5 Mbit) 0x000C 0000 - 0x000C 3FFF RESERVED 0x000C 4000 - 0x000E FFFF BLOCK 1 ROM (1.5 mbit) 0x000F 0000 - 0x000F BFFF RESERVED 0x000F C000 - 0x000F FFFF
SHORT WORD ADDRESSING
IOP REGISTERS 0x0000 0000 - 0x0003 FFFF BLOCK 0 SRAM (0.5 Mbit) 0x0010 0000 - 0x0010 7FFF RESERVED 0x0010 8000 - 0x0015 FFFF BLOCK 0 ROM (1.5 mbit) 0x0016 0000 - 0x0017 7FFF RESERVED 0x0017 8FFF - 0x0017 FFFF BLOCK 1 SRAM (0.5 Mbit) 0x0018 0000 - 0x0018 7FFF RESERVED 0x0018 8000 - 0x001D FFFF BLOCK 1 ROM (1.5 mbit) 0x001E 0000 - 0x001F 7FFF RESERVED 0x000
EXTERNAL MEMORY SPACE
RESERVED 0x0020 0000 - 0x00FF FFFF 1EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE BY THE CORE. DMA MUST BE USED TO READ OR WRITE TO THIS MEMORY USING THE SPI OR PARALLEL PORT. 2BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE (0x000A 0000 - 0x000A AAAA). 3BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE (0x000E 0000 - 0x000E AAA).
EXTERNAL DMA ADDRESS SPACE1 0x0100 0000 - 0x02FF FFFF
RESERVED 0x0300 0000 - 0x3FFF FFFF
Figure 3. ADSP-21267 Memory Map
* I2S mode * Left-justified sample pair mode Left-justified Sample Pair Mode is a mode where in each Frame Sync cycle two samples of data are transmitted/received -- one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over various attributes of this mode. Each of the serial ports supports the Left-justified Sample Pair and I2S protocols (I2S is an industry standard interface commonly used by audio codecs, ADCs and DACs such as the Analog Devices AD183x family), with two data pins, allowing four Left-justified Sample Pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 16 audio channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to
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32 bits. For the Left-justified Sample Pair and I2S modes, dataword lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional -law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated.
Serial Peripheral (Compatible) Interface
Serial Peripheral Interface (SPI) is an industry standard synchronous serial link, enabling the ADSP-21267 SPI-compatible port to communicate with other SPI-compatible devices. SPI is an interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multi-master environment by interfacing with up to four other SPI-compatible devices, either acting as a master or
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PRELIMINARY TECHNICAL DATA ADSP-21267
slave device. The ADSP-21267 SPI-compatible peripheral implementation also features programmable baud rates up to 37.5 MHz, clock phases, and polarities. The ADSP-21267 SPIcompatible port uses open drain drivers to support a multi-master configuration and to avoid data contention.
Phased Locked Loop
The ADSP-21267 uses an on-chip Phase Locked Loop (PLL) to generate the internal clock for the core. On power up, the CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1. After booting, numerous other ratios can be selected via software control. The ratios are made up of software configurable numerator values from 1 to 32 and software configurable divisor values of 1, 2, 4, 8, and 16.
Parallel Port
The Parallel Port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15-0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8- or 16bit, the maximum data transfer rate is one-third the core clock speed. As an example, for a clock rate of 150 MHz, this is equivalent to 50 Mbytes/sec. DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the parallel port register read/write functions. The RD, WR, and ALE (Address Latch Enable) pins are the control pins for the parallel port.
Power Supplies
The ADSP-21267 has separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply (AVDD) powers the ADSP-21267's clock generator PLL. To produce a stable clock, you should provide an external circuit to filter the power input to the AVDD pin. Place the filter as close as possible to the pin. For an example circuit, see Figure 4. To prevent noise coupling, use a wide trace for the analog ground (AVSS) signal and install a decoupling capacitor as close as possible to the pin. Note that the AVSS and AVDD pins specified in Figure 4 are inputs to the SHARC and not the analog ground plane on the board.
Timers
The ADSP-21267 has a total of four timers: a core timer able to generate periodic software interrupts and three general purpose timers that can that can generate periodic interrupts and be independently set to operate in one of three modes: * Pulse Waveform Generation mode * Pulse Width Count/Capture mode * External Event Watchdog mode The core timer can be configured to use FLAG3 as a Timer Expired output signal, and each general purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables all three general purpose timers independently.
10 VDDINT 0.1 F 0.01 F AVDD
AVSS
Figure 4. Analog Power (AVDD) Filter Circuit
ROM Based Security
The ADSP-21267 has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the DSP does not boot-load any external code, executing exclusively from internal SRAM/ROM. Additionally, the DSP is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or Test Access Port, will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned.
TARGET BOARD JTAG EMULATOR CONNECTOR
Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21267 processor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor's JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on Analog Devices' SHARC DSP Tools product line of JTAG emulator operation, see the appropriate emulator hardware user's guide.
Program Booting
The internal memory of the ADSP-21267 boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave or an internal boot. Booting is determined by the Boot Configuration (BOOTCFG1-0) pins. Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM.
DEVELOPMENT TOOLS
The ADSP-21267 is supported by a complete automotive reference design and development board as well as by a complete home audio reference design board available from Analog Devices. These boards implement complete audio decoding and post processing algorithms that are factory programmed into
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the ROM of the ADSP-21267. SIMD optimized libraries consume less processing resources, which results in more available processing power for custom proprietary features. The non-volatile memory of the ADSP-21267 can be configured to contain a combination of PCM 96 KHz, Dolby Digital, Dolby Digital EX2, Dolby Pro Logic IIx, DTS 5.1, DTS Matrix 6.1, DTS Discrete 6.1, DTS Neo:6, and MPEG2 2 channel. Multiple S/PDIF and analog I/Os are provided to maximize end system flexibility. The ADSP-21267 is supported with a complete set of CROSSCORETM software and hardware development tools, including Analog Devices emulators and VisualDSP++TM development environment. The same emulator hardware that supports other SHARC processors also fully emulates the ADSP-21267. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy to use assembler (which is based on an algebraic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The SHARC has architectural features that improve the efficiency of compiled C/C++ code. The VisualDSP++ debugger has a number of important features. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representation of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this capability can have increasing significance on the designer's development schedule, increasing productivity. Statistical profiling enables the programmer to non intrusively poll the processor as it is running the program. This feature, unique to VisualDSP++, enables the software developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify bottlenecks in software quickly and efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * View mixed C/C++ and assembly code (interleaved source and object information) * Insert breakpoints * Set conditional breakpoints on registers, memory, and stacks * Trace instruction execution * Perform linear or statistical profiling of program execution * Fill, dump, and graphically plot the contents of memory * Perform source level debugging * Create custom debugger windows The VisualDSP++ IDDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the SHARC development tools, including the color syntax highlighting in the VisualDSP++ editor. This capability permits programmers to: * Control how the development tools process inputs and generate outputs * Maintain a one-to-one correspondence with the tool's command line switches The VisualDSP++ Kernel (VDK) incorporates scheduling and resource management tailored specifically to address the memory and timing constraints of DSP programming. These capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. The VDK features include Threads, Critical and Unscheduled regions, Semaphores, Events, and Device flags. The VDK also supports Priority-based, Preemptive, Cooperative, and Time-Sliced scheduling approaches. In addition, the VDK was designed to be scalable. If the application does not use a specific feature, the support code for that feature is excluded from the target system. Because the VDK is a library, a developer can decide whether to use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard command line tools. When the VDK is used, the development environment assists the developer with many error-prone tasks and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the system state, when debugging an application that uses the VDK. VisualDSP++ Component Software Engineering (VCSE) is Analog Devices technology for creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software applications. Download components from the Web and drop them into the application. Publish component archives from within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language. Use the Expert Linker to visually manipulate the placement of code and data on the embedded system. View memory utilization in a color-coded graphical form, easily move code and data to different areas of the DSP or external memory with the drag of the mouse, examine run time stack and heap usage. The Expert Linker is fully compatible with existing Linker Definition File (LDF), allowing the developer to move between the graphical and textual environments. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the SHARC processor family. Hardware tools include SHARC processor PC plug-in cards. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
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DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET)
The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. Nonintrusive incircuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target board must include a header that connects the DSP's JTAG port to the emulator. For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices TAG Emulation Technical Reference on the Analog Devices website (www.analog.com). Use site search on "EE-68." This document is updated regularly to keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21267 architecture and functionality. For detailed information on the ADSP-2126x Family core architecture and instruction set, refer to the ADSP-2126x DSP Core Manual and the ADSP-21160 SHARC DSP Instruction Set Reference.
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PIN FUNCTION DESCRIPTIONS
ADSP-21267 pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Tie or pull unused inputs to VDDEXT or GND, except for the following: * DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI and AD15-0 (NOTE: These pins have internal pull-up resistors.) The following symbols appear in the Type column of Table 2: A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, and T = Three-State.
Table 2. Pin Descriptions
Pin AD15-0 Type I/O/T State During & After Reset Three-state with pull-up enabled Function
RD
O
WR
O
ALE
O
FLAG3-0
I/O/A
Parallel Port Address/Data. The ADSP-21267 parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 K internal pull-up resistor. See Address Data Modes on page 13 for details of the AD pin operation: For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper 16 external address bits, A23-8; ALE is used in conjunction with an external latch to retain the values of the A23-8. For 16-bit mode: ALE is automatically asserted whenever a change occurs in the address bits, A15-0; ALE is used in conjunction with an external latch to retain the values of the A15-0. To use these pins as flags (FLAG15-0) set (=1) bit 20 of the SYSCTL register and disable the parallel port. See Table 3 on page 13 for a list of how the AD15-0 pins map to the flag pins. When used as an input, the IDP Channel0 can use these pins for parallel input data. Output only, driven Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or 16high1 bit data from an external memory device. When AD15-0 are flags, this pin remains deasserted. Output only, driven Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or high1 16-bit data to an external memory device. When AD15-0 are flags, this pin remains deasserted. Output only, driven Parallel Port Address Latch enable. ALE is asserted whenever the DSP drives a new address on the parallel port address pins. On reset, ALE is active high. However, low1 it can be reconfigured using software to be active low. When AD15-0 are flags, this pin remains deasserted. Three-state Flag Pins. Each FLAG pin is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. These pins can be used as an SPI interface slave select output during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0. When bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1. When bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2. When bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP which indicates that the system timer has expired.
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Table 2. Pin Descriptions (Continued)
Pin DAI_P20-1 Type I/O/T State During & After Reset Three-state with programmable pullup Function Digital Audio Interface Pins. These pins provide the physical interface to the SRU. The SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin's output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the SRU may be routed to any of these pins. The SRU provides the connection from the Serial ports, Input data port, precision clock generators and timers to the DAI_P20-1 pins These pins have internal 22.5 K pull-up resistors which are enabled on reset. These pull-ups can be disabled in the DAI_PIN_PULLUP register. Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 22.5 K internal pull-up resistor. Serial Peripheral Interface Slave Device Select. An active low signal used to select the DSP as an SPI slave device. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multi-master mode the DSPs SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multi-master error. For a single-master, multiple-slave configuration where flag pins are used, this pin must be tied or pulled high to VDDEXT on the master device. For ADSP-21267 to ADSP-21267 SPI interaction, any of the master ADSP-21267's flag pins can be used to drive the SPIDS signal on the ADSP-21267 SPI slave device. SPI Master Out Slave In. If the ADSP-21267 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21267 is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an ADSP-21267 SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 K internal pull-up resistor. SPI Master In Slave Out. If the ADSP-21267 is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-21267 is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an ADSP-21267 SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has a 22.5K internal pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. To enable broadcast transmission to multiple SPI-slaves, the DSP's MISO pin may be disabled by setting (=1) bit 5 (DMISO) of the SPICTL register. Boot Configuration Select. Selects the boot mode for the DSP. The BOOTCFG pins must be valid before reset is asserted. See Table 4 on page 13 for a description of the boot modes.
SPICLK
I/O
Three-state with pull-up enabled
SPIDS
I
Input only
MOSI
I/O (O/D)
Three-state with pull-up enabled
MISO
I/O (O/D)
Three-state with pull-up enabled
BOOTCFG1-0
I
Input only
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Table 2. Pin Descriptions (Continued)
Pin CLKIN Type I State During & After Reset Input only Function Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21267 clock input. It configures the ADSP-21267 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21267 to use the external clock source such as an external clock oscillator. The core is clocked either by the PLL output or this clock input depending on the CLKCFG1-0 pin settings. CLKIN may not be halted, changed, or operated below the specified frequency. Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal. Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 5 on page 13 for a description of the clock configuration modes. Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. Reset Out/Local Clock Out. Drives out the core reset signal to an external device. CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can be switched between the PLL output clock and reset out by setting bit 12 of the PMCTL register. The default is reset out. Processor Reset. Resets the ADSP-21267 to a known state. Upon deassertion, there is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET input must be asserted (low) at power-up. Test Clock (JTAG). Provides a clock for JTAG boundary scan. must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21267. Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 22.5 k internal pull-up resistor. Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21267. TRST has a 22.5 k internal pull-up resistor. Emulation Status. Must be connected to the ADSP-21267 Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU has a 22.5 k internal pullup resistor. Core Power Supply. Nominally +1.2 V dc and supplies the DSP's core processor (13 pins on the BGA package, 32 pins on the LQFP package). I/O Power Supply. Nominally +3.3 V dc. (6 pins on the BGA package, 10 pins on the LQFP package). Analog Power Supply. Nominally +1.2 V dc and supplies the DSP's internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added filtering circuitry is required. For more information, see Power Supplies on page 7. Analog Power Supply Return. Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).
XTAL CLKCFG1-0
O I
Output only2 Input only
RSTOUT/CLKOUT
O
Output only
RESET
I/A
Input only
TCK TMS TDI TDO TRST
I I/S I/S O I/A
Input only3 Three-state with pull-up enabled Three-state with pull-up enabled Three-state4 Three-state with pull-up enabled Three-state with pull-up enabled
EMU
O (O/D)
VDDINT VDDEXT AVDD
P P P
AVSS GND
1 2
G G
RD, WR, and ALE are continuously driven by the DSP and won't be three-stated. Output only is a three-state driver with its output path always enabled. 3 Input only is three-state driver with both output path. 4 Three-state is three-state driver.
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ADDRESS DATA PINS AS FLAGS
To use these pins as flags (FLAG15-0) set (=1) bit 20 of the SYSCTL register and disable the parallel port. Table 3. AD[15:0] to FLAG Pin Mapping
AD Pin AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Flag Pin FLAG8 FLAG9 FLAG10 FLAG11 FLAG12 FLAG13 FLAG14 FLAG15 FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7
deasserted. For 16-bit data transfers, ALE latches address bits A15-A0 when asserted, followed by data bits D15-D0 when deasserted. Table 6. Address/ Data Mode Selection
EP Data Mode 8-bit 8-bit 16-bit 16-bit ALE Asserted Deasserted Asserted Deasserted AD7-0 Function A15-8 D7-0 A7-0 D7-0 AD15-8 Function A23-16 A7-0 A15-8 D15-8
Boot Modes
Table 4. Boot Mode Selection
BOOTCFG1-0 00 01 10 11 Booting Mode SPI Slave Boot SPI Master Boot Parallel Port boot via EPROM Internal Boot Mode (ROM code only)
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
Table 5. Core Instruction Rate/ CLKIN Ratio Selection
CLKCFG1-0 00 01 10 11 Core to CLKIN Ratio 3:1 16:1 8:1 Reserved
ADDRESS DATA MODES
The following table shows the functionality of the AD pins for 8-bit and 16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches address bits A23-A8 when asserted, followed by address bits A7-A0 and data bits D7-D0 when
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ADSP-21267 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade Parameter1 VDDINT AVDD VDDEXT VIH VIL TAMB
1 2
Min Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage2, @ VDDEXT = max Low Level Input Voltage2 @ VDDEXT = min Ambient Operating Temperature3 4 1.14 1.14 3.13 2.0 -0.5 0
Max 1.26 1.26 3.47 VDDEXT+0.5 0.8 +70
Unit V V V V V C
Specifications subject to change without notice. Applies to input and bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKIN, CLKCFGx, RESET, TCK, TMS, TDI, TRST. 3 See Thermal Characteristics on page 37 for information on thermal specifications. 4 See Engineer-to-Engineer Note (No. 216) for further information.
ELECTRICAL CHARACTERISTICS
Parameter1 VOH VOL IIH IIL IILPU IOZH IOZL IOZLPU IDD-INTYP AIDD CIN
1 2
High Level Output Voltage2 Low Level Output Voltage2 High Level Input Current4, 5 Low Level Input Current4 Low Level Input Current Pull-Up5 Three-State Leakage Current 6, 7, 8 Three-State Leakage Current6 Three-State Leakage Current Pull-Up7 Supply Current (Internal)9, 10, 11 Supply Current (Analog)12 Input Capacitance13, 14
Test Conditions @ VDDEXT = min, IOH = -1.0 mA3 @ VDDEXT = min, IOL = 1.0 mA3 @ VDDEXT = max, VIN = VDDEXT max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 0 V @ VDDEXT= max, VIN = VDDEXT max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 0 V tCCLK = 5.0 ns, VDDINT = 1.2V, TAMB = +25C AVDD = max fIN=1 MHz, TCASE=25C, VIN=1.2V
Min 2.4
Max 0.4 10 10 200 10 10 200 500 10 4.7
Unit V V A A A A A A mA mA pF
Specifications subject to change without notice. Applies to output and bidirectional pins: AD15-0, RD, WR, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL. 3 See Output Drive Currents on page 36 for typical drive current capabilities. 4 Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN. 5 Applies to input pins with 22.5 K internal pull-ups: TRST, TMS, TDI. 6 Applies to three-statable pins: FLAG3-0. 7 Applies to three-statable pins with 22.5 kK pull-ups: AD15-0, DAI_Px, SPICLK, MISO, MOSI. 8 Applies to open-drain output pins: EMU, MISO, MOSI. 9 Typical internal current data reflects nominal operating conditions. 10 See Engineer-to-Engineer Note (No. 216) for further information. 11 Characterized, but not tested. 12 Characterized, but not tested. 13 Applies to all signal pins. 14 Guaranteed, but not tested.
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ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDDINT)1 Analog (PLL) Supply Voltage (AVDD)1 External (I/O) Supply Voltage (VDDEXT)1 Input Voltage Output Voltage Swing Load Capacitance1 Storage Temperature Range1 Junction Temperature under Bias
1
-0.3 V to +1.4 V -0.3 V to +1.4 V -0.3 V to +3.8 V -0.5 V to VDDEXT1 + 0.5 V -0.5 V to VDDEXT1 + 0.5 V 200 pF -65C to +150C 125C
Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21267 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS
The ADSP-21267's internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP's internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1-0 pins. To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports).
The ADSP-21267's internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP's internal clock (the clock source for the parallel port logic and I/O pads). Note the definitions of various clock periods that are a function of CLKIN and the appropriate ratio control (Table 7).
Table 7. ADSP-21267 CLKOUT and CCLK Clock Generation Operation
Timing Requirements CLKIN CCLK Timing Requirements tCK tCCLK tSCLK tSPICLK
1
Description Input Clock Core Clock Description1 CLKIN Clock Period (Processor) Core Clock Period Serial Port Clock Period = (tCCLK) x SR SPI Clock Period = (tCCLK) x SPIR
Calculation 1/tCK 1/tCCLK
where: SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV) SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register) DAI_Px = Serial Port Clock SPICLK = SPI Clock
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Figure 5 shows Core to CLKIN ratios of 3:1, 8:1 and 16:1 with external oscillator or crystal. Note that more ratios are possible and can be set through software using the power management control register (PMCTL). For more information, see the ADSP2126x SHARC DSP Core Manual.
CLKOUT CLKIN XTAL XTAL OSC PLLILCLK PLL 3:1, 8:1, 16:1 CCLK (CORE CLOCK)
CLK-CFG [1:0]
Figure 5. Core Clock and System Clock Relationship to CLKIN
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 30 on page 36 under Test Conditions for voltage reference levels. Switching Characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. The ADSP-21267's internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP's internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1-0 pins. To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports). The ADSP-21267's internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP's internal clock (the clock source for the parallel port logic and I/O pads). Note the following definitions of various clock periods that are a function of CLKIN and the appropriate ratio control.
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Power up Sequencing
The timing requirements for DSP startup are given in Table 8. Table 8. Power Up Sequencing Timing Requirements (DSP Startup)
Parameter Timing Requirements tRSTVDD tIVDDEVDD tCLKVDD tCLKRST tPLLRST tWRST Min RESET low before VDDINT/VDDEXT on VDDINT on before VDDEXT CLKIN valid after VDDINT/VDDEXT valid1 CLKIN valid before RESET deasserted PLL control setup before RESET deasserted Subsequent RESET low pulse width4 0 -50 0 102 203 4tCK Max Unit ns ms ms s s ns
200 200
Switching Characteristic tCORERST DSP core reset deasserted after RESET deasserted
1
4096tCK 4,5
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time. Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Based on CLKIN cycles 4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and propagate default states at all I/O pins. 5 The 4096 cycle count depends on tSRST specification in Table 10. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 cycles maximum.
2
R ES E T
tR S T V D D
V D D IN T
tIV D D E V D D
V D D EX T
tC L K V D D
C LK IN
tC L K R S T
C LK _C FG 1-0
t PL L R S T
R ST O U T*
tC O R E R S T
*M U LTIP LE X ED W ITH C LK O U T
Figure 6. Power Up Sequencing
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Clock Input
Table 9. Clock Input
Parameter Timing Requirements tCK CLKIN Period tCKL CLKIN Width Low tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4V-2.0V) tCCLK CCLK Period3
1
150 MHz Min 201 7.51 7.51 6.66
Max 1602 802 802 3 10
200 MHz Min 151 61 61 5
Unit Max 1602 802 802 3 10 ns ns ns ns ns
Applies only for CLKCFG1-0 = 00 and default values for PLL control bits in PMCTL. 2 Applies only for CLKCFG1-0 = 01 and default values for PLL control bits in PMCTL. 3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
tCK CLKIN tCKH tCKL
CLKIN
1M
XTAL
C1
X1
C2
Figure 7. Clock Input
Clock Signals
The ADSP-21267 can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21267 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 8 shows the component connections used for a crystal operating in fun-
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
Figure 8. 150 MHz or 200 MHz Operation (Fundamental Mode Crystal)
Reset
Table 10. Reset
Parameter Timing Requirements tWRST RESET Pulse Width Low1 RESET Setup Before CLKIN Low tSRST
1
Min 4tCK 8
Max
Unit ns ns
Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN tWRST RESET tSRST
Figure 9. Reset
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Interrupts
The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P[20:1] pins when configured as interrupts. Table 11. Interrupts
Parameter Timing Requirement tIPW IRQx Pulse Width Min 2 x tCCLK +2 Max Unit ns
DAI_P[20:1] (FLG2-0) (IRQ2-0)
tIPW
Figure 10. Interrupts
Core Timer
The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER). Table 12. Core Timer
Parameter Switching Characteristic tWCTIM CTIMER Pulse Width Min 4 x tCCLK Max Unit ns
FLG3 (C T IM E R )
t W C T IM
Figure 11. Core Timer
Rev. PrA |
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January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer[2:0] in PWM_OUT (pulse width modulation) mode. Timer signals are routed to the DAI_P[20:1] pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins. Table 13. Timer[2:0] PWM_OUT Timing
Parameter Switching Characteristic tPWMO Timer[2:0] Pulse Width Output Min 2 tCCLK Max 2(231 - 1) tCCLK Unit ns
tPWMO DAI_P[20:1] (TIMER[2:0])
Figure 12. Timer[2:0] PWM_OUT Timing
Timer WDTH_CAP Timing
The following timing specification applies to Timer[2:0] in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P[20:1] pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins. Table 14. Timer[2:0] Width Capture Timing
Parameter Timing Requirement tPWI Timer[2:0] Pulse Width Min 2 tCCLK Max 2(231 - 1) tCCLK Unit ns
tPWI DAI_P[20:1] (TIMER[2:0])
Figure 13. Timer[2:0] Width Capture Timing
Rev. PrA |
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January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
DAI Pin to Pin Direct Routing
For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 15. DAI Pin to Pin Routing
Parameter Timing Requirement tDPIO Delay DAI Pin Input Valid to DAI Output Valid Min 3 Max 10 Unit ns
DAI_Pn
DAI_Pm
tDPIO
Figure 14. DAI Pin to PIN Direct Routing
Rev. PrA |
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January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that the Precision Clock Generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG's Table 16. Precision Clock Generator (Direct Pin Routing)
Parameter Timing Requirements tPCGIW Input Clock Pulse Width tSTRIG PCG Trigger Setup Before Falling Edge of PCG Input Clock PCG Trigger Hold After Falling Edge of PCG Input Clock tHTRIG Min 20 2 2 Max Unit ns ns ns
inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is not timing data available. All Timing Parameters and Switching Characteristics apply to external DAI pins (DAI_P07 - DAI_P20).
Switching Characteristics PCG Output Clock and Frame Sync Active Edge Delay After PCG Input tDPCGIO Clock Falling Edge 2.5 tDTRIG PCG Output Clock and Frame Sync Delay After PCG Trigger 2.5 + 2.5 x tPCGOW Output Clock Pulse Width 40 tPCGOW
10 ns 10 + 2.5 x tPCGOW ns ns
tSTRIG
DAI_Pn PCG_TRIGx_I tHTRIG DAI_Pm PCG_EXTx_I (CLKIN) DAI_Py PCG_CLKx_O tDPCGIO tPCGIW
tPCGOW DAI_Pz PCG_FSx_O tDTRIG
Figure 15. Precision Clock Generator (Direct Pin Routing)
Rev. PrA |
Page 22 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Flags
The timing specifications provided below apply to the FLAG[3:0] and DAI_P[20:1] pins, the parallel port and the serial peripheral interface (SPI). See Table 2, "Pin Descriptions," on page 10 for more information on flag use. Table 17. Flags
Parameter Timing Requirement tFIPW FLAG[3:0] IN Pulse Width Switching Characteristic tFOPW FLAG[3:0] OUT Pulse Width Min 2 x tCCLK+3 Max Unit ns
2 x tCCLK - 1
ns
DAI_P[20:1] (FLG3-0IN) (AD[15:0])
tFIPW
DAI_P[20:1] (FLG3-0OUT) (AD[15:0])
tFOPW
Figure 16. Flags
Rev. PrA |
Page 23 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Memory Read-Parallel Port
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21267 is accessing external memory space. Table 18. 8-Bit Memory Read Cycle
Parameter Timing Requirements Address/Data [7:0] Setup Before RD High tDRS tDRH Address/Data [7:0] Hold After RD High tDAD Address [15:8] to Data Valid Switching Characteristics tALEW ALE Pulse Width tALERW ALE Deasserted to Read/Write Asserted tADAS Address/Data [15:0] Setup Before ALE Deasserted1 tADAH Address/Data [15:0] Hold After ALE Deasserted1 ALE Deasserted1 to Address/Data[7:0] In High Z tALEHZ tRW RD Pulse Width tADRH Address/Data [15:8] Hold After RD High D = (Data Cycle Duration) x tCCLK H= tCCLK (if a hold cycle is specified, else H = 0)
1
Min 3.3 0
Max
Unit ns ns ns
D + 0.5 x tCCLK - 3.5
2 x tCCLK - 2 1 x tCCLK - 1 2.5 x tCCLK - 2.0 0.5 x tCCLK - 0.8 0.5 x tCCLK - 0.8 D-2 0.5 x tCCLK - 1 + H
0.5 x tCCLK + 3.0
ns ns ns ns ns ns ns
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALE
tALEW tALERW
RD
tRW
WR
tALEHZ tADAS tADAH tADRH
AD[15:8]
VALID ADDRESS
VALID ADDRESS tDRS tDRH
AD[7:0]
VALID ADDRESS
tDAD
VALID DATA
Figure 17. Read Cycle For 8-bit Memory Timing
Rev. PrA |
Page 24 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Table 19. 16-bit Memory Read Cycle
Parameter Timing Requirements tDRS tDRH Min Address/Data [15:0] Setup Before RD high Address/Data [15:0] Hold After RD high 3.3 0 Max Unit ns ns ns ns ns ns ns ns ns
Switching Characteristics tALEW ALE Pulse Width ALE Deasserted to Read/Write Asserted tALERW tADAS Address/Data [15:0] Setup Before ALE Deasserted1 tADAH Address/Data [15:0] Hold After ALE Deaserted1 tALEHZ ALE Deasserted1 to Address/Data[15:0] In High Z tRW RD Pulse Width D = (Data Cycle Duration) x tCCLK H = tCCLK (if a hold cycle is specified, else H = 0)
1
2 x tCCLK - 2 1 x tCCLK - 1 2.5 x tCCLK - 2.0 0.5 x tCCLK - 0.8 0.5 x tCCLK - 0.8 D-2
0.5tCCLK + 3.0
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALE
tALEW tALERW
RD
tRW
WR
tADAS AD[15:0] VALID ADDRESS
tADAH
tDRS
tDRH
VALID DATA tALEHZ
Figure 18. Read Cycle For 16-bit Memory Timing
Rev. PrA |
Page 25 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Memory Write--Parallel Port
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21267 is accessing external memory space. Table 20. 8-bit Memory Write Cycle
Parameter Switching Characteristics: ALE Pulse Width tALEW tALERW ALE Deasserted to Read/Write Asserted tADAS Address/Data [15:0] Setup Before ALE Deasserted1 tADAH Address/data [15:0] Hold After ALE Deasserted1 tWW WR Pulse Width tADWL Address/Data [15:8] to WR Low Address/Data [15:8] hold after WR High tADWH tALEHZ ALE Deasserted1 to Address/Data[15:0] In High Z tDWS Address/Data [7:0] Setup Before WR High tDWH Address/Data [7:0] Hold After WR High tDAWH Address/Data to WR High D = (Data Cycle Duration) x tCCLK H = tCCLK (if a hold cycle is specified, else H = 0)
1
Min 2 x tCCLK - 2 1 x tCCLK - 1 2.5 x tCCLK - 2.0 0.5 x tCCLK - 0.8 D-2 0.5 x tCCLK - 1.5 0.5 x tCCLK - 1 + H 0.5 x tCCLK - 0.8 D 0.5 x tCCLK - 1.5 + H D
Max
Unit ns ns ns ns ns ns ns ns ns ns ns
0.5tCCLK + 3.0
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
tALERW ALE tALEW tDAWH
WR
tWW
RD
tALEHZ tADAS tADAH
tADWL
tADWH
AD[15:8]
VALID ADDRESS
VALID ADDRESS tDWS tDWH
AD[7:0]
VALID ADDRESS
VALID DATA
Figure 19. Write Cycle For 8-bit Memory Timing
Rev. PrA |
Page 26 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Table 21. 16-bit Memory Write Cycle
Parameter Switching Characteristics tALEW ALE Pulse Width ALE Deasserted to Read/Write Asserted tALERW tADAS Address/Data [15:0] Setup Before ALE Deasserted1 tADAH Address/Data [15:0] Hold After ALE Deasserted1 tWW WR Pulse Width tALEHZ ALE Deasserted1 to Address/Data[15:0] In High Z tDWS Address/Data [15:0] Setup Before WR High tDWH Address/Data [15:0] Hold After WR High D = (Data Cycle Duration) x tCCLK H = tCCLK (if a hold cycle is specified, else H = 0)
1
Min 2 x tCCLK - 2 1 x tCCLK - 1 2.5 x tCCLK - 2.0 0.5 x tCCLK - 0.8 D-2 0.5 x tCCLK - 0.8 D 0.5 x tCCLK - 1.5 + H
Max
Unit ns ns ns ns ns ns ns ns
0.5tCCLK + 3.0
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALE
tALEW tALERW
WR
tWW
RD
tALEHZ tADAS tADAH tDWS tDWH
AD[15:0]
VALID ADDRESS
VALID DATA
Figure 20. Write Cycle For 16-bit Memory Timing
Rev. PrA |
Page 27 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Serial Ports
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 22. Serial Ports--External Clock
Parameter Timing Requirements tSFSE FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode)1 tHFSE FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive Mode)1 tSDRE Receive Data Setup Before Receive SCLK1 tHDRE Receive Data Hold After SCLK1 tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE FS Delay After SCLK (Internally Generated FS in Ether Transmit or Receive Mode) 2 tHOFSE FS Hold After SCLK (Internally Generated FS in Either Transmit or Receive Mode2) tDDTE Transmit Data Delay After Transmit SCLK2 tHDTE Transmit Data Hold After Transmit SCLK2
1 2
Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P[20:1] pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins.
Min
Max
Unit
2.5 2.5 2.5 2.5 7 20
ns ns ns ns ns ns
7 2 7 2
ns ns ns ns
Referenced to sample edge. Referenced to drive edge.
Table 23. Serial Ports--Internal Clock
Parameter Timing Requirements tSFSI FS Setup Before SCLK (Externally Generated FS in Either Transmit or Receive Mode)1 tHFSI FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive Mode)1 tSDRI Receive Data Setup Before SCLK1 tHDRI Receive Data Hold After SCLK1 Switching Characteristics tDFSI FS Delay After SCLK (Internally Generated FS in Transmit Mode)2 FS Hold After SCLK (Internally Generated FS in Transmit Mode)2 tHOFSI tDFSI FS Delay After SCLK (Internally Generated FS in Receive or Mode)2 tHOFSI FS Hold After SCLK (Internally Generated FS in Receive Mode)2 tDDTI Transmit Data Delay After SCLK2 tHDTI Transmit Data Hold After SCLK2 tSCLKIW Transmit or Receive SCLK Width
1 2
Min
Max
Unit
6 1.5 6 1.5
ns ns ns ns
3 -1.0 3 -1.0 3 -1.0 0.5tSCLK - 2 0.5tSCLK + 2
ns ns ns ns ns ns ns
Referenced to the sample edge. Referenced to drive edge.
Rev. PrA |
Page 28 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Table 24. Serial Ports--Enable and Three-State
Parameter Switching Characteristics tDDTEN Data Enable from External Transmit SCLK1 Data Disable from External Transmit SCLK1 tDDTTE tDDTIN Data Enable from Internal Transmit SCLK1
1
Min 2
Max
Unit ns ns ns
7 -1
Referenced to drive edge.
Table 25. Serial Ports--External Late Frame Sync
Parameter Min Switching Characteristics tDDTLFSE Data Delay from Late External Transmit FS or External Receive FS with MCE = 1, MFD = 01 tDDTENFS Data Enable for MCE = 1, MFD = 01 0.5
1
Max
Unit
7
ns ns
The tDDTLFSE and tDDTENFS parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DIA_P[20:0] (SCLK) DRIVE SAMPLE tHFSE/I tSFSE/I DIA_P[20:0] (FS) tDDTENFS DIA_P[20:0] (DXA/DXB) tDDTLFSE tHDTE/I 1ST BIT 2ND BIT tDDTE/I DRIVE
LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE tHFSE/I DRIVE
DIA_P[20:0] (SCLK)
tSFSE/I DIA_P[20:0] (FS)
tDDTENFS DIA_P[20:0] (DXA/DXB) tDDTLFSE tHDTE/I 1ST BIT
tDDTE/I
2ND BIT
NOTE SERIAL PORT SIGNALS (SCLK, FS, DXA,/DXB) ARE ROUTED TO THE DAI_P[20:1] PINS USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.
Figure 21. External Late Frame Sync1
1
This figure reflects changes made to support Left-justified Sample Pair mode.
Rev. PrA |
Page 29 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
DATA RECEIVE-- INTERNAL CLOCK DRIVE EDGE tSCLKIW DAI_P[20:1] (SCLK) tDFSI tHOFSI DAI_P[20:1] (FS) tSDRI DAI_P[20:1] (DXA/DXB) tHDRI DAI_P[20:1] (DXA/DXB) tSFSI tHFSI DAI_P[20:1] (FS) DAI_P[20:1] (SCLK) SAMPLE EDGE
DATA RECEIVE-- EXTERNAL CLOCK DRIVE EDGE tSCLKW SAMPLE EDGE
tDFSE tHOFSE tSFSE
tHFSE
tSDRE
tHDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT -- INTERNAL CLOCK DRIVE EDGE tSCLKIW DAI_P[20:1] (SCLK) tDFSI tHOFSI DAI_P[20:1] (FS) tHDTI DAI_P[20:1] (DXA/DXB) tDDTI DAI_P[20:1] (DXA/DXB) tSFSI tHFSI DAI_P[20:1] (FS) DAI_P[20:1] (SCLK) SAMPLE EDGE
DATA TRANSMIT -- EXTERNAL CLOCK DRIVE EDGE tSCLKW SAMPLE EDGE
tDFSE tHOFSE tSFSE tHFSE
tHDTE
tDDTE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE DAI_P[20:1] SCLK (EXT) tDDTEN DAI_P[20:1] DXA/DXB DRIVE EDGE DAI_P[20:1] SCLK (INT) SCLK tDDTTE
DRIVE EDGE
tDDTIN
DAI_P[20:1] DXA/DXB
Figure 22. Serial Ports
Rev. PrA |
Page 30 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 26. IDP Signals (SCLK, FS, SDATA) are routed to the DAI_P[20:1] pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins. Table 26. Input Data Port
Parameter Timing Requirements tSISFS FS Setup Before SCLK Rising Edge1 tSIHFS FS Hold After SCLK Rising Edge1 SData Setup Before SCLK Rising Edge1 tSISD tSIHD SData Hold After SCLK Rising Edge1 tIDPCLKW Clock Width tIDPCLK Clock Period
1
Min 2.5 2.5 2.5 2.5 7 20
Max
Unit ns ns ns ns ns ns
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the Precision Clock Generators (PCG) or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SAMPLE EDGE tIDPCLKW DAI_P[20:1] (SCLK) tSIHFS
tSISFS DAI_P[20:1] (FS) tSISD DAI_P[20:1] (SDATA)
tSIHD
Figure 23. IDP Master Timing
Rev. PrA |
Page 31 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in Table 27. PDAP is the parallel mode operation of channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2126x Hardware Reference Manual. Note Table 27. Parallel Data Acquisition Port (PDAP)
Parameter Timing Requirements tSPCLKEN PDAP_CLKEN Setup Before PDAP_CLK Sample Edge1 tHPCLKEN PDAP_CLKEN Hold After PDAP_CLK Sample Edge1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge1 tPDSD tPDHD PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge1 tPDCLKW Clock Width tPDCLK Clock Period Switching Characteristics tPDHLDD Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word tPDSTRB PDAP Strobe Pulse Width
1
that the most significant 16 bits of external PDAP data can be provided through either the parallel port AD[15:0] or the DAI_P[20:5] pins. The remaining 4 bits can only be sourced through DAI_P[4:1]. The timing below is valid at the DAI_P[20:1] pins or at the AD[15:0] pins.
Min 2.5 2.5 2.5 2.5 7 20
Max
Unit ns ns ns ns ns ns
2 x tCCLK 1 x tCCLK - 1
ns ns
Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
SAMPLE EDGE tPDCLKW DAI_P[20:1] (PDAP_CLK) tSPCLKEN DAI_P[20:1] (PDAP_CLKEN) tPDSD DATA tPDHD tHPCLKEN
DAI_P[20:1] (PDAP_STROBE)
tPDSTRB tPDHLDD
Figure 24. PDAP Timing
Rev. PrA |
Page 32 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
SPI Interface--Master
Table 28. SPI Interface Protocol -- Master Switching and Timing Specifications
Parameter Timing Requirements tSSPIDM Data input valid to SPICLK edge (data input set-up time) tHSPIDM SPICLK Last Sampling Edge to Data Input Not Valid Switching Characteristics tSPICLKM Serial Clock Cycle tSPICHM SeriaL Clock High Period tSPICLM SeriaL Clock Low Period tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) FLAG3-0 OUT (SPI Device Select) Low to First SPICLK Edge tSDSCIM tHDSM Last SPICLK Edge to FLAG3-0 OUT High tSPITDM Sequential Transfer Delay Min 5 2 Max Unit ns ns
8 x tCCLK 4 x tCCLK - 2 4 x tCCLK - 2 3 10 4 x tCCLK - 2 4 x tCCLK - 1 4 x tCCLK - 1
ns ns ns ns ns ns ns ns
FLG3-0 (OUTPUT)
tS D S C I M
SPICLK (CP = 0) (OUTPUT)
tS P I C H M
t S P IC LM
t S P IC LK M
tHDSM
tS P I T D M
t S P IC LM
SPICLK (CP = 1) (OUTPUT)
tS P I C H M
tDDSPIDM
MOSI (OUTPUT) MSB
t HDSPIDM
LSB
t S S P ID M
CPHASE = 1 MISO (INPUT) MSB VALID
tSSPIDM tHSPIDM
LSB VALID
tHSPIDM
tDDSPIDM
MOSI (OUTPUT) CPHASE = 0 MISO (INPUT) MSB
tHDSPIDM
LSB
tSSPIDM
MSB VALID
t H S P ID M
LSB VALID
Figure 25. SPI Master Timing
Rev. PrA |
Page 33 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
SPI Interface--Slave
Table 29. SPI Interface Protocol --Slave Switching and Timing Specifications
Parameter Timing Requirements tSPICLKS tSPICHS tSPICLS tSDSCO Min Serial Clock Cycle Serial Clock High Period Serial Clock Low Period SPIDS Assertion to First SPICLK Edge CPHASE = 0 CPHASE = 1 Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0 Data Input Valid to SPICLK Edge (Data Input Set-up Time) SPICLK Last Sampling Edge to Data Input Not Valid SPIDS Deassertion Pulse Width (CPHASE=0) 4 x tCCLK 2 x tCCLK - 2 2 x tCCLK - 2 2 x tCCLK + 1 2 x tCCLK + 1 2 x tCCLK 2 2 2 x tCCLK Max Unit ns ns ns ns ns ns ns ns ns
tHDS tSSPIDS tHSPIDS tSDPPW
Switching Characteristics tDSOE SPIDS Assertion to Data Out Active tDSDHI SPIDS Deassertion to Data High Impedance tDDSPIDS SPICLK Edge to Data Out Valid (Data Out Delay Time) SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tHDSPIDS tDSOV SPIDS Assertion to Data Out Valid (CPHASE=0)
0 0 2 x tCCLK - 2
5 5 7.5 5 x tCCLK + 2
ns ns ns ns ns
SPIDS (INPUT)
t S P IC H S
SPICLK (CP = 0) (INPUT)
tSPICLS
tSPICL KS tHDS tSDPPW
tSDSCO
SPICLK (CP = 1) (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPIDS tDDSPIDS
MSB LSB
tDSDHI tHDSPIDS
MISO (OUTPUT) CPHASE = 1 MOSI (INPUT)
tHSPIDS tSSPIDS
MSB VALID
tSSPIDS
LSB VALID
tDSOV tD S O E
MISO (OUTPUT) CPHASE = 0 MOSI (INPUT) MSB
tDDSPIDS
tHDSPIDS
tDSDHI
LSB
tSSPIDS
MSB VALID LSB VALID
tHSPIDS
Figure 26. SPI Slave Timing
Rev. PrA |
Page 34 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
JTAG Test Access Port and Emulation
Table 30. JTAG Test Access Port and Emulation
Parameter Timing Requirements tTCK TCK Period tSTAP TDI, TMS Setup Before TCK High tHTAP TDI, TMS Hold After TCK High tSSYS System Inputs Setup Before TCK Low1 tHSYS System Inputs Hold After TCK Low1 tTRSTW TRST Pulse Width Switching Characteristics tDTDO TDO Delay from TCK Low System Outputs Delay After TCK Low2 tDSYS
1 2
Min 20 5 6 7 8 4tCK
Max
Unit ns ns ns ns ns ns
7 10
ns ns
System Inputs = AD15-0, SPIDS, CLKCFG1-0, RESET, BOOTCFG1-0, MISO, MOSI, SPICLK, DAI_Px, FLAG3-0 System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15-0, RD, WR, FLAG3-0, CLKOUT, EMU, ALE.
tTCK TCK tSTAP TMS TDI tDTDO TDO tSSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS tHSYS tHTAP
Figure 27. IEEE 11499.1 JTAG Test Access Port
Rev. PrA |
Page 35 of 44 |
January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
OUTPUT DRIVE CURRENTS
Figure 28 shows typical I-V characteristics for the output drivers of the ADSP-21267. The curves represent the current drive capability of the output drivers as a function of output voltage.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads: 12 pF on all pins (see Figure 29). Figure 32 shows graphically how output delays and holds vary with load capacitance (Note that this graph or derating does not apply to output disable delays. The graphs of Figure 31, Figure 32 and Figure 33 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20%-80%, V=Min) vs. Load Capacitance.
40 30
SOURCE (VDDEXT) CURRENT - mA
VOH TBD
20 10 0
12.0
10.0
RISE AND FALL TIMES - ns
-10 -20 -30 -40 0 0.5 1 1.5 2 2.5 SWEEP (VDDEXT ) VOLTAGE - V 3 3.5 V OL TBD
8.0
TBD
6.0
4.0
Figure 28. ADSP-21267 Typical Drive
2.0
TEST CONDITIONS
The ac signal specifications (timing parameters) appear Table 9 on page 18 through Table 30 on page 35. These include output disable time, output enable time, and capacitive loading. Timing is measured on signals when they cross the 1.5 V level as described in Figure 30 on page 36. All delays (in nanoseconds) are measured between the point that the first signal reaches 1.5 V and the point that the second signal reaches 1.5 V.
RISE AND FALL TIMES - ns
0 0 20 40 60 80 100 120 LOAD CAPACITANCE - PF
Figure 31. Typical Output Rise Time (20%-80%, VDDEXT = Max)
12
10 8
TO OUTPUT PIN 30pF
50 1.5V
6 4 2
TBD
Figure 29. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
0 0 20 40 60 80 100 120
LOAD CAPACITANCE - pF
INPUT OR OUTPUT 1.5V 1.5V
Figure 32. Typical Output Rise/Fall Time (20%-80%, VDDEXT = Min)
Figure 30. Voltage Reference Levels for AC Measurements
Rev. PrA |
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January 2004
PRELIMINARY TECHNICAL DATA ADSP-21267
Where:
7 6
OUTPUT DELAY OR HOLD - ns
TA = Ambient Temperature 0C Values of JC are provided for package comparison and PCB design considerations when an external heatsink is required. Values of JB are provided for package comparison and PCB design considerations.
TBD
5 4 3 2 1 0 -1 -2 -3 -4 0 20 40 60 80 100 120
Table 31. Thermal Characteristics for 136 Ball BGA
Parameter JA JMA JMA JB JC JT JMT JMT Condition Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Typical 28.2 24.4 23.3 20.1 7.0 0.1 0.3 0.4 Unit C/W C/W C/W C/W C/W C/W C/W C/W
LOAD CAPACITANCE - pF
Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature)
Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s
ENVIRONMENTAL CONDITIONS
The ADSP-21267 processor is rated for performance over the commercial temperature range, TAMB = 0C to 70C. Table 32. Thermal Characteristics for 144 Lead LQFP
Parameter JA JMA JMA JC JT JMT JMT Typical 32.5 28.9 27.8 7.8 0.5 0.8 1.0 Unit C/W C/W C/W C/W C/W C/W C/W
THERMAL CHARACTERISTICS
The ADSP-21267 is offered in 144-lead LQFP and 136-ball BGA packages Table 31 and Table 32 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-toboard measurement complies with JESD51-8. The junction-tocase measurement complies with MIL- STD-883. All measurements use a 2S2P JEDEC test board. To determine the Junction Temperature of the device while on the application PCB, use: T J = T CASE + ( JT x PD ) Where: TJ= Junction temperature 0C TCASE= Case temperature (0C) measured at the top center of the package JT= Junction-to-Top (of package) characterization parameter = Typical value from the tables below PD= Power dissipation see EE Note #216 Values of JA are provided for package comparison and PCB design considerations. JA can be used for a 1st order approximation of TJ by the equation: T J = T A + ( JA x PD )
Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s
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PRELIMINARY TECHNICAL DATA ADSP-21267
136-BALL BGA PIN CONFIGURATIONS
The following table shows the ADSP-21267's pin names and their default function after reset (in parenthesis). Table 33. 136-ball BGA Pin Assignments
Pin Name CLKCFG0 XTAL TMS TCK TDI CLKOUT TDO EMU MOSI MISO SPIDS VDDINT GND GND VDDINT GND GND GND GND GND GND GND GND FLAG3 BGA Pin# A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 E01 E02 E04 E05 E06 E09 E10 E11 E13 E14 Pin Name CLKCFG1 GND VDDEXT CLKIN TRST AVSS AVDD VDDEXT SPICLK RESET VDDINT GND GND GND FLAG1 FLAG0 GND GND GND GND GND GND FLAG2 DAI_P20 (SFS45) BGA Pin# B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 F01 F02 F04 F05 F06 F09 F10 F11 F13 F14 Pin Name BOOTCFG1 BOOTCFG0 GND GND GND VDDINT BGA Pin# C01 C02 C03 C12 C13 C14 Pin Name VDDINT GND GND GND GND GND GND GND GND VDDINT BGA Pin# D01 D02 D04 D05 D06 D09 D10 D11 D13 D14
AD7 VDDINT VDDEXT DAI_P19 (SCLK45)
G01 G02 G13 G14
AD6 VDDEXT DAI_P18 (SD5B) DAI_P17 (SD5A)
H01 H02 H13 H14
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PRELIMINARY TECHNICAL DATA ADSP-21267
Table 33. 136-ball BGA Pin Assignments (Continued)
Pin Name AD5 AD4 GND GND GND GND GND GND VDDINT DAI_P16 (SD4B) AD15 ALE RD VDDINT VDDEXT AD8 VDDINT DAI_P2 (SD0B) VDDEXT DAI_P4 (SFS0) VDDINT VDDINT GND DAI_P10 (SD2B) BGA Pin# J01 J02 J04 J05 J06 J09 J10 J11 J13 J14 N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 Pin Name AD3 VDDINT GND GND GND GND GND GND GND DAI_P15 (SD4A) AD14 AD13 AD12 AD11 AD10 AD9 DAI_P1 (SD0A) DAI_P3 (SCLK0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) DAI_P8 (SFS1) DAI_P9 (SD2A) DAI_P11 (SD3A) BGA Pin# K01 K02 K04 K05 K06 K09 K10 K11 K13 K14 P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 Pin Name AD2 AD1 GND GND GND GND GND GND GND DAI_P14 (SFS23) BGA Pin# L01 L02 L04 L05 L06 L09 L10 L11 L13 L14 Pin Name AD0 WR GND GND DAI_P12 (SD3B) DAI_P13 (SCLK23) BGA Pin# M01 M02 M03 M12 M13 M14
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PRELIMINARY TECHNICAL DATA ADSP-21267
14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P
KEY
VDDINT VDDEXT GND* AVSS AVDD I/O SIGNALS
*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD'S GROUND PLANE.
Figure 34. 136-ball BGA Pin Assignments (Bottom View, Summary)
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PRELIMINARY TECHNICAL DATA ADSP-21267
144-LEAD LQFP PIN CONFIGURATIONS
The following table shows the ADSP-21267's pin names and their default function after reset (in parenthesis). Table 34. 144-Lead LQFP Pin Assignments
Pin Name VDDINT CLKCFG0 CLKCFG1 BOOTCFG0 BOOTCFG1 GND VDDEXT GND VDDINT GND VDDINT GND VDDINT GND FLAG0 FLAG1 AD7 GND VDDINT GND VDDEXT GND VDDINT AD6 AD5 AD4 VDDINT GND AD3 AD2 VDDEXT GND AD1 AD0 WR VDDINT LQFP Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name VDDINT GND RD ALE AD15 AD14 AD13 GND VDDEXT AD12 VDDINT GND AD11 AD10 AD9 AD8 DAI_P1 (SD0A) VDDINT GND DAI_P2 (SD0B) DAI_P3 (SCLK0) GND VDDEXT VDDINT GND DAI_P4 (SFS0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) VDDINT GND VDDINT GND DAI_P8 (SFS1) DAI_P9 (SD2A) VDDINT LQFP Pin # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 LQFP Pin # VDDEXT 73 GND 74 VDDINT 75 GND 76 DAI_P10 (SD2B) 77 DAI_P11 (SD3A) 78 DAI_P12 (SD3B) 79 DAI_P13 (SCLK23) 80 DAI_P14 (SFS23) 81 DAI_P15 (SD4A) 82 VDDINT 83 GND 84 GND 85 DAI_P16 (SD4B) 86 DAI_P17 (SD5A) 87 DAI_P18 (SD5B) 88 DAI_P19 (SCLK45) 89 VDDINT 90 GND 91 GND 92 VDDEXT 93 DAI_P20 (SFS45) 94 GND 95 VDDINT 96 FLAG2 97 FLAG3 98 VDDINT 99 GND 100 101 VDDINT GND 102 VDDINT 103 GND 104 VDDINT 105 GND 106 VDDINT 107 VDDINT 108 Pin Name Pin Name GND VDDINT GND VDDINT GND VDDINT GND VDDEXT GND VDDINT GND VDDINT RESET SPIDS GND VDDINT SPICLK MISO MOSI GND VDDINT VDDEXT AVDD AVSS GND CLKOUT EMU TDO TDI TRST TCK TMS GND CLKIN XTAL VDDEXT LQFP Pin # 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
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PRELIMINARY TECHNICAL DATA ADSP-21267
PACKAGE DIMENSIONS
The ADSP-21267 is available in a 136-ball BGA package and a 144-lead LQFP package. All dimensions are in millimeters (mm).
Figure 35. 136-ball BGA
12.00 SQ BSC
A1 BALL PAD CORNER
0.80 TYP
A B C D E F G H J K L M N P
10.40 BSC
A1 BALL PAD CORNER
Top View
12.00 SQ BSC
10.40 BSC
14 13 12 11 10 9 8 7 6 5 4 3 2 1 DETAIL A 1.70 MAX
0.80 TYP
DETAIL A 1.31 1.21 1.10 0.25 MIN 0.50 0.46 0.40 BALL DIAMETER 0.12 MAX SEATING PLANE
ALL DIMENSIONS IN MILIMETERS (MM). 1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.150 MM OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 MM OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID. 2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205-AE WITH THE EXCEPTION OF DIMENSION "b"
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PRELIMINARY TECHNICAL DATA ADSP-21267
Figure 36. 144-lead LQFP (ST-144)
22.00 BSC SQ 20.00 BSC SQ
144 1 109 108
PIN 1 INDICATOR 0.27 0.22 TYP 0.17 0.50 BSC TYP (LEAD PITCH)
SEATING PLANE 0.08 MAX (LEAD COPLANARITY) 0.15 0.05 1.45 1.40 1.35 1.60 MAX NOTES: 1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-026-BFB. 2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION. 3. CENTER DIMENSIONS ARE NOMINAL.
36 73
0.75 0.60 TYP 0.45
37
72
DETAIL A
DETAIL A
TOP VIEW (PINS DOWN)
ORDERING GUIDE
Analog Devices offers a wide variety of audio algorithms and combinations to run on the ADSP-21267 DSP. These products are sold as part of a chip set, bundled with necessary application software under special part numbers. For a complete list, visit our web site at www.analog.com\SHARC.
Part Number1,2,3 ADSP-21267SKSTZ-X ADSP-21267SKBCZ-X
1 2
These product also may contain 3rd party IPs that may require users to have authorization from the respective IP holders to receive them. Royalty for use of the 3rd party IPs may also be payable by users.
Ambient Temperature Range 0C to +70C 0C to +70C
Instruction Rate On-Chip SRAM 150 MHz 1 Mbit 150 MHz 1 Mbit
ROM 3 Mbit 3 Mbit
Operating Voltage Package 1.2 INT/3.3 EXT V 1.2 INT/3.3 EXT V 144-Lead LQFP 136-Lead BGA
K indicates commercial grade temperature (0C to +70C). B indicates Ball Grid Array package. ST indicates Low Profile Quad Flat package. 3 Z indicates Lead Free package. For more information about lead free package offerings, please visit www.analog.com.
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PRELIMINARY TECHNICAL DATA ADSP-21267
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR04623-0-1/04(PrA)
a
Page 44 of 44 | January 2004
www.analog.com
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